CHIPS R&D Standards Summit, 62545-62546 [2023-19645]

Download as PDF Federal Register / Vol. 88, No. 175 / Tuesday, September 12, 2023 / Notices DEPARTMENT OF COMMERCE National Institute of Standards and Technology Additive Construction by Extrusion (ACE) Consortium National Institute of Standards and Technology, Department of Commerce. ACTION: Notice of research consortium. AGENCY: The National Institute of Standards and Technology (NIST), an agency of the United States Department of Commerce, in support of efforts to establish the measurement science required for development of the standards and industry for Additive Construction by Extrusion (ACE), is establishing the Additive Construction by Extrusion (ACE) Consortium (‘‘Consortium’’). The Consortium will bring together stakeholders to identify and address gaps in current standards related to materials, methods, structural performance, and engineering design. The Consortium efforts are intended to study the measurement science needs for the successful adoption of ACE by the construction industry, and to identify and propose new standards to address industry needs not met by existing standards. Participation fees will be at least $10,000 annually or inkind contributions of equivalent value. Participants will be required to sign a Cooperative Research and Development Agreement (CRADA). At NIST’s discretion, entities which are not permitted to enter into CRADAs pursuant to law or other governmental constraint may be allowed to participate in the Consortium pursuant to a separate non-CRADA agreement. DATES: The Consortium’s activities will commence on October 15, 2023 (‘‘Commencement Date’’). NIST will accept letters of interest to participate in this Consortium on an ongoing basis. ADDRESSES: Completed letters of interest or requests for additional information about the Consortium can be directed via mail to the Consortium Manager, Dr. Shawn Platt, Materials and Structural Systems Division of NIST’s Engineering Laboratory, 100 Bureau Drive, Mail Stop 8615, Gaithersburg, Maryland 20899, or via electronic mail to shawn.platt@ nist.gov. lotter on DSK11XQN23PROD with NOTICES1 SUMMARY: FOR FURTHER INFORMATION CONTACT: J’aime Maynard, Consortia Agreements Officer, National Institute of Standards and Technology’s Technology Partnerships Office, by telephone at (301) 975–8408, by mail to 100 Bureau Drive, Mail Stop 2200, Gaithersburg, VerDate Sep<11>2014 17:32 Sep 11, 2023 Jkt 259001 Maryland 20899, or by electronic mail to Jaime.maynard@nist.gov. SUPPLEMENTARY INFORMATION: Additive construction by extrusion (ACE) technology has the potential to revolutionize the construction industry by eliminating the need for formwork and enabling architectural and structural designs that cannot be achieved through current standard practices. As ACE remains in the early stages of development, this Consortium will study the measurement science needs for the successful adoption of ACE by the construction industry. The objective of this Consortium is to identify and then translate cementitious material measurements to in-line or inprocess measurements for quality control and quality assurance in the ACE process. Participants in the Consortium will work with NIST toward the following goals: (1) Correlating Off-Line Measurements to Print Quality A focus will be on correlating off-line measurements of fresh and hardening ink to a measure of print quality. The objectives are to determine material performance characteristics that are critical to the success of ACE. (2) In-Situ and In-Process Measurements A focus will be on developing in-situ and in-process measurements that may be used to provide feedback into the control of the ACE process. The objective is to implement material property measurements in line to the ACE process. (3) Hardened Properties and Scaling up From Paste to Concrete A focus will be on measurements at the structural scale, including a proper consideration of in-field issues. This includes, but is not limited to, hardened property measurements; studies on curing practices and finishing procedures; and development of numerical simulations of material deposition. The objectives are to develop measurement techniques to assess hardened properties of 3–D printed structures and investigate how early age properties and measurements may inform ACE through the use of numerical simulations. Participation Process NIST is soliciting responses from all sources, including other Federal Government agencies, State or local governments, foreign government agencies, industrial organizations (including corporations, partnerships, and limited partnerships, and industrial PO 00000 Frm 00022 Fmt 4703 Sfmt 4703 62545 development organizations), public and private foundations, and nonprofit organizations (including universities). Eligibility will be determined by NIST based on the information provided by prospective participants in response to this notice. NIST will evaluate the submitted responses from prospective participants to determine eligibility to participate in this Consortium. Prospective participants should provide letters of interest with the following information to NIST’s Consortium Manager: 1. Narrative of interest in ACE and description of related experience and expertise to contribute to the Consortium. 2. List of anticipated participating individuals. 3. If proposing in-kind participation instead of a fee contribution, description of anticipated in-kind donation and its equivalent value to fee. Letters of interest must not include business proprietary information. NIST will not treat any information provided in response to this notice as proprietary information. NIST will notify each organization of its eligibility. In order to participate in this Consortium, each eligible organization must sign a CRADA for this Consortium. Entities which are not permitted to enter into CRADAs pursuant to law or other governmental constraint may be allowed to participate in the Consortium, at NIST’s discretion, pursuant to separate non-CRADA agreements with terms that may differ, as necessary, from the Consortium CRADA terms. Participants will contribute US $10,000 annually in funds or equivalent in-kind contributions to be members of the Consortium. NIST does not guarantee participation in the Consortium to any organization submitting a letter of interest. This phase of the Consortium will be for up to five years. Authority: 15 U.S.C. 3710a. Alicia Chambers, NIST Executive Secretariat. [FR Doc. 2023–19647 Filed 9–11–23; 8:45 am] BILLING CODE 3510–13–P DEPARTMENT OF COMMERCE National Institute of Standards and Technology CHIPS R&D Standards Summit CHIPS Research and Development Office (CHIPS R&D Office), National Institute of Standards and Technology (NIST), Department of Commerce. AGENCY: E:\FR\FM\12SEN1.SGM 12SEN1 62546 ACTION: Federal Register / Vol. 88, No. 175 / Tuesday, September 12, 2023 / Notices Notice of public meeting. The National Institute of Standards and Technology (NIST) announces that the CHIPS Research and Development Office (CHIPS R&D Office) will hold a Standards Summit on Tuesday, September 26, 2023 and Wednesday, September 27, 2023, from 8:30 a.m. to 5:30 p.m. Eastern Time each day. The CHIPS R&D Standards Summit will be held as an in-person and virtual event. This event will bring together CHIPS R&D leaders, standards setting organizations, and industry alliances, domestic and abroad, in the semiconductor domain to identify community priorities for semiconductor and microelectronics standards activities. The summit will be a place to foster collaboration, coordination, and innovation within the semiconductor industry’s standards community. This event will facilitate discussions on standards needs, opportunities for standards innovation, and enabling a diverse standards-capable workforce. Registration information, summit updates, and the agenda can be found at https://www.nist.gov/news-events/ events/2023/09/chips-rd-standardssummit. DATES: The CHIPS R&D Standards Summit will take place on Tuesday, September 26, 2023, and Wednesday, 27, 2023, from 8:30 a.m. to 5:30 p.m. Eastern Time each day. The summit will require prior registration and is open to the public. Registration for both virtual and in-person will close on Tuesday, September 19, 2023 at 11:59 p.m. Eastern Time. ADDRESSES: The CHIPS R&D Standards Summit will be held in person and virtually via web conference from the Capitol Hilton located at 1001 16th St. NW, Washington, DC 20036. Registration is required to participate either in person or virtually, and members of the public should register in accordance with the information provided in the SUPPLEMENTARY INFORMATION section of this notice. FOR FURTHER INFORMATION CONTACT: For more information about the CHIPS R&D Standards Summit, please contact Chris Greer by telephone at (301) 975–5919 or by email at christopher.greer@nist.gov. SUPPLEMENTARY INFORMATION: The CHIPS R&D Standards Summit will bring together thought leaders within the semiconductor industry and academia to shape the future of semiconductor and microelectronics standards and drive innovation. The summit will offer sessions that facilitate consensus building on the top priority areas within the industry, ways to lotter on DSK11XQN23PROD with NOTICES1 SUMMARY: VerDate Sep<11>2014 17:32 Sep 11, 2023 Jkt 259001 accelerate strategic efforts across these priority areas, and cover concepts from incubators and accelerators as practiced in the technology sector that might be adapted for use in standards development and enabling a diverse, standards-capable workforce. The summit’s first day will consist of plenary and panel sessions with exemplary keynote and guest speakers in the semiconductor and microelectronics standards space. The following day will consist of breakout sessions where attendees will collaborate and discuss key topics that will help shape future semiconductor and microelectronics standards activities. Participants will explore ways to improve the agility and efficiency of the standards process, ensuring its continued growth in the rapidly evolving semiconductor industry. The scope of the summit includes the full range of standards types—including best practices, de facto, and formal standards—while spanning the semiconductor and microelectronics sector, from materials and design to fabrication, packaging, and testing and certification. Featured speakers include CHIPS R&D leaders, representatives of standards setting organizations, and leading industry alliances and consortia. Co-hosted by the CHIPS R&D Office, the American National Standards Institute (ANSI), the IEEE Industry Standards and Technology Organization (IEEE–ISTO), the International Electronics Manufacturing Initiative (iNEMI), IPC International, the Joint Development Foundation (JDF), the Networking and Information Technology Research and Development Program (NITRD), the National Nanotechnology Coordination Office (NNCO), SEMI North America, and the Semiconductor Industry Association (SIA), the summit will bring together key stakeholders and experts to exchange ideas on focusing and accelerating strategic efforts across the full spectrum of standards development pathways. The outcomes of the CHIPS R&D Standards Summit will shape future stakeholder meetings and inform strategies for the CHIPS R&D Office. They will also provide input to standards and measurement programs supporting the needs of the semiconductor industry, enhancing innovation and technology advancement. These outcomes will be published in a post-summit report and will inform standards planning efforts across the semiconductor innovation ecosystem and within the CHIPS R&D Office. PO 00000 Frm 00023 Fmt 4703 Sfmt 9990 We encourage interested stakeholders, industry representatives, and standards setting organizations to participate actively in this pivotal event. We also invite international attendees, as fostering global collaboration and enriching the discussions on advancing semiconductor standards and innovation is paramount to success. Join us at the CHIPS R&D Standards Summit as we collaboratively shape the future of semiconductor and microelectronics standards, foster innovation, and advance the industry as a whole. Registration Information: The CHIPS R&D Standards Summit is available for guests to attend in person in Washington, DC, or virtually via a web conference platform. Registration for all attendees is on a first-come, first-served basis. An in-person registration fee of $41 includes all-day coffee, tea and bottled beverages. There is no registration fee to attend virtually. Once the event has reached capacity for registration, additional registrants will be added to a waitlist. All attendees will participate in the keynote, plenary, and breakout sessions. In-person guests will participate in live discussions during the various sessions. Virtual guests can contribute to discussions via Q&A and conversation tools on the web conference platform. On the summit registration form, attendees must select whether to attend in person or virtually. Attendees must also provide their full name, contact information, company name and title, and any accessibility accommodation requests. Registration for in-person and virtual attendance options will close on Tuesday, September 19, 2023 at 11:59 p.m. Eastern Time. For more information and to register for the event, visit the CHIPS R&D Standards Summit website at https://www.nist.gov/news-events/ events/2023/09/chips-rd-standardssummit. About CHIPS for America CHIPS for America includes the CHIPS Program Office, responsible for semiconductor incentives, and the CHIPS Research and Development Office, responsible for R&D programs. Both sit within the National Institute of Standards and Technology (NIST) at the Department of Commerce. Alicia Chambers, NIST Executive Secretariat. [FR Doc. 2023–19645 Filed 9–11–23; 8:45 am] BILLING CODE 3510–13–P E:\FR\FM\12SEN1.SGM 12SEN1

Agencies

[Federal Register Volume 88, Number 175 (Tuesday, September 12, 2023)]
[Notices]
[Pages 62545-62546]
From the Federal Register Online via the Government Publishing Office [www.gpo.gov]
[FR Doc No: 2023-19645]


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DEPARTMENT OF COMMERCE

National Institute of Standards and Technology


CHIPS R&D Standards Summit

AGENCY: CHIPS Research and Development Office (CHIPS R&D Office), 
National Institute of Standards and Technology (NIST), Department of 
Commerce.

[[Page 62546]]


ACTION: Notice of public meeting.

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SUMMARY: The National Institute of Standards and Technology (NIST) 
announces that the CHIPS Research and Development Office (CHIPS R&D 
Office) will hold a Standards Summit on Tuesday, September 26, 2023 and 
Wednesday, September 27, 2023, from 8:30 a.m. to 5:30 p.m. Eastern Time 
each day. The CHIPS R&D Standards Summit will be held as an in-person 
and virtual event. This event will bring together CHIPS R&D leaders, 
standards setting organizations, and industry alliances, domestic and 
abroad, in the semiconductor domain to identify community priorities 
for semiconductor and microelectronics standards activities. The summit 
will be a place to foster collaboration, coordination, and innovation 
within the semiconductor industry's standards community. This event 
will facilitate discussions on standards needs, opportunities for 
standards innovation, and enabling a diverse standards-capable 
workforce. Registration information, summit updates, and the agenda can 
be found at https://www.nist.gov/news-events/events/2023/09/chips-rd-standards-summit.

DATES: The CHIPS R&D Standards Summit will take place on Tuesday, 
September 26, 2023, and Wednesday, 27, 2023, from 8:30 a.m. to 5:30 
p.m. Eastern Time each day. The summit will require prior registration 
and is open to the public. Registration for both virtual and in-person 
will close on Tuesday, September 19, 2023 at 11:59 p.m. Eastern Time.

ADDRESSES: The CHIPS R&D Standards Summit will be held in person and 
virtually via web conference from the Capitol Hilton located at 1001 
16th St. NW, Washington, DC 20036. Registration is required to 
participate either in person or virtually, and members of the public 
should register in accordance with the information provided in the 
SUPPLEMENTARY INFORMATION section of this notice.

FOR FURTHER INFORMATION CONTACT: For more information about the CHIPS 
R&D Standards Summit, please contact Chris Greer by telephone at (301) 
975-5919 or by email at [email protected].

SUPPLEMENTARY INFORMATION: The CHIPS R&D Standards Summit will bring 
together thought leaders within the semiconductor industry and academia 
to shape the future of semiconductor and microelectronics standards and 
drive innovation. The summit will offer sessions that facilitate 
consensus building on the top priority areas within the industry, ways 
to accelerate strategic efforts across these priority areas, and cover 
concepts from incubators and accelerators as practiced in the 
technology sector that might be adapted for use in standards 
development and enabling a diverse, standards-capable workforce. The 
summit's first day will consist of plenary and panel sessions with 
exemplary keynote and guest speakers in the semiconductor and 
microelectronics standards space. The following day will consist of 
breakout sessions where attendees will collaborate and discuss key 
topics that will help shape future semiconductor and microelectronics 
standards activities.
    Participants will explore ways to improve the agility and 
efficiency of the standards process, ensuring its continued growth in 
the rapidly evolving semiconductor industry. The scope of the summit 
includes the full range of standards types--including best practices, 
de facto, and formal standards--while spanning the semiconductor and 
microelectronics sector, from materials and design to fabrication, 
packaging, and testing and certification. Featured speakers include 
CHIPS R&D leaders, representatives of standards setting organizations, 
and leading industry alliances and consortia.
    Co-hosted by the CHIPS R&D Office, the American National Standards 
Institute (ANSI), the IEEE Industry Standards and Technology 
Organization (IEEE-ISTO), the International Electronics Manufacturing 
Initiative (iNEMI), IPC International, the Joint Development Foundation 
(JDF), the Networking and Information Technology Research and 
Development Program (NITRD), the National Nanotechnology Coordination 
Office (NNCO), SEMI North America, and the Semiconductor Industry 
Association (SIA), the summit will bring together key stakeholders and 
experts to exchange ideas on focusing and accelerating strategic 
efforts across the full spectrum of standards development pathways.
    The outcomes of the CHIPS R&D Standards Summit will shape future 
stakeholder meetings and inform strategies for the CHIPS R&D Office. 
They will also provide input to standards and measurement programs 
supporting the needs of the semiconductor industry, enhancing 
innovation and technology advancement. These outcomes will be published 
in a post-summit report and will inform standards planning efforts 
across the semiconductor innovation ecosystem and within the CHIPS R&D 
Office.
    We encourage interested stakeholders, industry representatives, and 
standards setting organizations to participate actively in this pivotal 
event. We also invite international attendees, as fostering global 
collaboration and enriching the discussions on advancing semiconductor 
standards and innovation is paramount to success. Join us at the CHIPS 
R&D Standards Summit as we collaboratively shape the future of 
semiconductor and microelectronics standards, foster innovation, and 
advance the industry as a whole.
    Registration Information: The CHIPS R&D Standards Summit is 
available for guests to attend in person in Washington, DC, or 
virtually via a web conference platform. Registration for all attendees 
is on a first-come, first-served basis. An in-person registration fee 
of $41 includes all-day coffee, tea and bottled beverages. There is no 
registration fee to attend virtually. Once the event has reached 
capacity for registration, additional registrants will be added to a 
waitlist. All attendees will participate in the keynote, plenary, and 
breakout sessions. In-person guests will participate in live 
discussions during the various sessions. Virtual guests can contribute 
to discussions via Q&A and conversation tools on the web conference 
platform. On the summit registration form, attendees must select 
whether to attend in person or virtually. Attendees must also provide 
their full name, contact information, company name and title, and any 
accessibility accommodation requests. Registration for in-person and 
virtual attendance options will close on Tuesday, September 19, 2023 at 
11:59 p.m. Eastern Time. For more information and to register for the 
event, visit the CHIPS R&D Standards Summit website at https://www.nist.gov/news-events/events/2023/09/chips-rd-standards-summit.

About CHIPS for America

    CHIPS for America includes the CHIPS Program Office, responsible 
for semiconductor incentives, and the CHIPS Research and Development 
Office, responsible for R&D programs. Both sit within the National 
Institute of Standards and Technology (NIST) at the Department of 
Commerce.

Alicia Chambers,
NIST Executive Secretariat.
[FR Doc. 2023-19645 Filed 9-11-23; 8:45 am]
BILLING CODE 3510-13-P

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